Silicon Quality and Reliability Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide.

• Perform end-to-end electrical and physical failure analysis on Central Processing Unit/Tensor Processing Unit (CPU/TPU) devices from prototype stages through manufacturing.
• Utilize advanced hardware and software techniques, such as Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH), to localize defects within reasoning and memory blocks.
• Execute destructive techniques including delayering, cross-sectioning, and high-resolution imaging (e.g., Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM), Focused Ion Beam (FIB)) to visualize and identify physical defects.
• Partner with design, product, and foundry teams to interpret failure data and implement actions for design or process improvements.
• Generate Failure Analysis (FA) reports and develop novel workflows tailored for advanced technology nodes and three-dimensional (3D) packaging architectures.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in semiconductor failure analysis or a related process engineering role.
• Experience with standard failure analysis lab equipment (e.g., Curve Tracer, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM)).
• Preferred qualifications: Experience with Chip-on-Wafer-on-Substrate (CoWoS) packaging, interconnect analysis or stress diagnostics.
• Experience with advanced diagnostics tools (e.g., Utilizing scan diagnosis, Automatic Test Pattern Generation (ATPG)), and memory Built-In Self-Test (BIST) tools for fault isolation.
• Experience with CPU/TPU specializations, diagnosing architecture-specific symptoms including cache bit flips, scanning chain issues, and Serializer/Deserializer Input/Output (SerDes I/O) failures.
• Experience with stress diagnostics.
• Knowledge of semiconductor device physics, transistor operation (e.g., Fin Field-Effect Transistor/Gate-All-Around Field-Effect Transistor (FinFET/GAA)), and fabrication processes.

• 401k matching
• Health insurance
• Flight privileges

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.