Senior SOC and IP Design Engineer, Google Cloud

Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks. Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up. Participate in test plan and coverage analysis of the block and SOC-level verification. Communicate and work with multi-disciplined and multi-site teams.

Responsibilities not listed.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
• Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
• Experience in reasoning design and debug with Design Verification (DV).
• Experience with a scripting language like Python or Perl.
• Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
• Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
• Knowledge of design techniques.
• Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.

• Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
• Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
• Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.
• Communicate and work with multi-disciplined and multi-site teams.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.