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SRAM Circuit Design Engineer

Apple

Beaverton, Oregon, U.S.
Full-time, Regular
Posted Oct 28, 2025
Onsite

Compensation

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About the role

Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, work with a team of hardworking engineers, and implement groundbreaking techniques of Machine Learning, Circuit design in Apple's marquee products like M1 and A14 Bionic.

Responsibilities

  • Design and implement custom digital circuits for SRAM design
  • Work with an extraordinary logic/architecture team to formulate design specifications
  • Define architecture/topologies optimizing for power, timing, area and yield
  • Schematic capture, simulations/analysis, margin verifications
  • Functional equivalency and DFT modeling
  • Work with layout team to create optimal GDS
  • Verify extracted GDS meets design specifications
  • Backend verification, IR/EM
  • Write RTL, validate use-cases, verify against design schematics
  • Support post-silicon effort to enable productization

Requirements

  • BS and a minimum of 10 years of relevant industry experience
  • Preferred Qualifications: Work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage and high performance
  • Knowledge of Cache design/architecture, memory hierarchy is a huge plus
  • Working knowledge of RTL modeling
  • Solid understanding of industry-standard design tools
  • Deep understanding of nanometer device physics, leakage mechanisms, technology interactions with device behavior
  • Ability to devise experiments and analyze data for silicon debug
  • Machine Learning algorithms (ML) and scripting is a big plus

Benefits

  • Design and implement custom digital circuits for SRAM design
  • Work with an extraordinary logic/architecture team to formulate design specifications
  • Define architecture/topologies optimizing for power, timing, area and yield
  • Schematic capture, simulations/analysis, margin verifications
  • Functional equivalency and DFT modeling
  • Work with layout team to create optimal GDS
  • Verify extracted GDS meets design specifications
  • Backend verification, IR/EM
  • Write RTL, validate use-cases, verify against design schematics
  • Support post-silicon effort to enable productization

Job Details

Salary Range

Salary not disclosed

Location

Beaverton, Oregon, U.S.

Employment Type

Full-time, Regular

Original Posting

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