Principal Design Engineer

Own and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including: Mixed-signal IPs, High-speed interfaces, Die-to-Die (D2D) communication links, Ensure IP designs meet stringent power, performance, and timing goals.

• Own and drive the development of microarchitecture and RTL design, coding, and verification of complex IP blocks, including: Mixed-signal IPs, High-speed interfaces, Die-to-Die (D2D) communication links, Ensure IP designs meet stringent power, performance, and timing goals.
• Develop constraints, power intent, synthesis, and perform static checks such as: LINT, CDC (Clock Domain Crossing), DRC (Design Rule Checking), Develop basic test benches.
• Support verification, DFT (Design for Test), and post-silicon validation activities in collaboration with verification and product teams.
• Collaborate effectively with: Architects, Analog mixed-signal designers, Verification engineers, Physical design and DFT teams, Other front-end designers, Align development methodologies with broader teams.
• Drive continuous improvement of RTL development processes for scalable execution.

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• 7+ years of experience in Digital Design, encompassing microarchitecture specification, RTL coding (Verilog/SystemVerilog), CDC/Lint closure, synthesis, timing constraints, PPA trade-offs, post-silicon debug, and successful delivery of IP and ASIC/SoC designs.
• 7+ years of experience in high-speed digital design and Die-to-Die (D2D) interfaces, including clocking, serialization, and signal integrity considerations.
• 7+ years of experience with automation using scripts PERL, Python or similar
• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
• Experience in one or more of the following areas: High Speed Serial or wide parallel Interfaces such as Ethernet/PCIe/USB or DDDR PHY IPs, Controller (such as ARM, RISCV) based designs, DSP, IXPACT-Based RTL Generation, Magillum Connectivity tool.

• Industry leading healthcare
• Educational resources
• Discounts on products and services
• Savings and investments
• Maternity and paternity leave
• Generous time away
• Giving programs
• Opportunities to network and connect

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.