Power UPF Methodology Engineer

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including: Drive Mixed signal IP power ERC and power intent verification. Drive coverage of power intent across static and dynamic checking methodologies. Define and develop power ERC framework for new projects. Bring up power intent checking flows on new projects. Drive power intent & power ERC sign-off for tape-out. Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues.

• Apply engineering fundamentals and groundbreaking efforts to bring forward-thinking ideas to the real world
• Design tools that allow customers to experience new things
• Integrate and come up with new insights
• Work with a team of hardworking engineers
• Develop and support transistor level power ERC sign-off for digital and mixed signal designs
• Drive power ERC sign-off at full-chip level
• Drive UPF implementation and verification for mobile SOCs
• Make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products

• A minimum of a bachelor's degree in relevant field
• A minimum of 10 years of relevant industry experience
• Experience in ASIC design methodology and an emphasis on power definition
• Experience in ASIC design flows and custom IP design flows
• Familiarity with Caliber based ERC flows
• Familiarity with power intent definition, implementation and verification flows
• Knowledge of scripting languages like, Tcl, Perl and Python
• Familiarity with of power analysis and optimization methods
• Familiarity with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking)

• Comprehensive medical and dental coverage
• Retirement benefits
• Range of discounted products and free services
• Reimbursement for certain educational expenses
• Discretionary bonuses or commission payments
• Relocation assistance

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.