Physical Design Engineer

As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines.

• Generate block/chip level static timing constraints
• Build full chip floor-plan including pin placement, partitions and power grid
• Develop and validate high performance low power clock network guidelines
• Perform block level place and route and close the design to meet timing, area and power constraints
• Generate and Implement ECOs to fix timing, noise and EM IR violations
• Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers
• Participate in establishing CAD and physical design methodologies for correct by construction designs
• Assist in flow development for chip integration

• BS and a minimum of 20 years relevant industry experiences
• Deep design experience in high PHY and/or SOC designs
• Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses

At Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer.